NXP Semiconductors /LPC5410x /CT32B2 /CCR

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Interpret as CCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CAP0RE)CAP0RE 0 (CAP0FE)CAP0FE 0 (CAP0I)CAP0I 0 (CAP1RE)CAP1RE 0 (CAP1FE)CAP1FE 0 (CAP1I)CAP1I 0 (CAP2RE)CAP2RE 0 (CAP2FE)CAP2FE 0 (CAP2I)CAP2I 0 (CAP3RE)CAP3RE 0 (CAP3FE)CAP3FE 0 (CAP3I)CAP3I 0RESERVED

Description

Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

Fields

CAP0RE

Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP0FE

Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP0I

Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt.

CAP1RE

Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP1FE

Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP1I

Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt.

CAP2RE

Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP2FE

Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP2I

Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt.

CAP3RE

Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP3FE

Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with the contents of TC. 0 = disabled. 1 = enabled.

CAP3I

Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt.

RESERVED

Reserved. Read value is undefined, only zero should be written.

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